In recent years, the gallium nitride base semiconductor device such as a GaN base HEMT or the like has been expected to be applied to highly high-power and high-speed devices because of its physical characteristics. In order to improve in high frequency characteristics of the GaN base semiconductor devices, a via wiring structured unit is necessary for the reduction of source inductance and the heat radiation.
A conventional method of manufacturing a GaN base HEMT will be explained here. FIG. 1A to FIG. 1X are sectional views showing the conventional method of manufacturing a GaN base HEMT in process order.
First, as shown in FIG. 1A, a GaN layer 102 and an n-type AlGaN layer 103 are formed over a surface of an insulating substrate 101 made of silicon carbide (SiC) in this order. The insulating substrate 101 is about 350 μm in thickness, and the total thickness of the GaN layer 102 and the n-type AlGaN layer 103 is about 2 μm. Then, a source electrode 104s, a gate electrode 104g and a drain electrode 104d are selectively formed on the n-type AlGaN layer 103. Thereafter, a SiN layer 105 covering the source electrode 104s, the gate electrode 104g and the drain electrode 104d is formed over the n-type AlGaN layer 103.
Then, as shown in FIG. 1B, a resist pattern 151 provided with an opening 151s corresponding to the source electrode 104s and an opening 151d corresponding to the drain electrode 104d is formed over the SiN 105. The resist pattern 151 is about 1 μm in thickness.
Next, as shown in FIG. 1C, a contact hole 105s matching to the opening 151s is formed above the source electrode 104s, and a contact hole 105d matching to the opening 151d is formed above the drain electrode 104d by patterning the SiN layer 105 using the resist pattern 151 as a mask.
Then, the resist pattern 151 is removed, and a resist pattern 152 provided with an opening 152s which is smaller than the opening 151s and corresponding to the source electrode 104s is newly formed over the SiN layer 105 and the source electrode 104s as shown in FIG. 1D. The resist pattern 152 is about 1 μm in thickness. The diameter of the opening 152s is about 150 μm.
Next, as shown in FIG. 1E, an opening 106 is formed by ion-milling the source electrode 104s using the resist pattern 152 as a mask.
Thereafter, the resist pattern 152 is removed, and, as shown in FIG. 1F, a stacked body composed of a titanium (Ti) layer and a nickel (Ni) layer, or a titanium (Ti) layer and a copper (Cu) layer is formed as a seed layer 107 over the whole surface on the front side of the insulating substrate 101.
Then, as shown in FIG. 1G, a resist pattern 153 provided with an opening 153s corresponding to the outer periphery of the source electrode 104s is formed over the seed layer 107. The thickness of the resist pattern 153 is about 3 μm. Then, a nickel (Ni) layer 108 of about 1.2 μm in thickness is formed on the seed layer 107 in the inside of the opening 153s by electroplating.
Then, as shown in FIG. 1H, the resist pattern 153 is removed.
Therefore, as shown in FIG. 1I, by ion-milling, a portion of the seed layer 107 exposed from the nickel (Ni) layer 108 is removed. The nickel (Ni) layer 108 is also processed a little simultaneously, and the resultant thickness of the nickel (Ni) layer 108 is about 1 μm.
Then, as shown in FIG. 1J, a stacked body composed of a titanium (Ti) layer, a platinum (Pt) layer and a gold (Au) layer is formed as a seed layer 109 over the whole surface on the front side of the insulating substrate 101.
Next, as shown in FIG. 1K, a resist pattern 154 provided with an opening corresponding to the outer periphery of the source electrode 104s and an opening corresponding to the outer periphery of the drain electrode 104d is formed over the seed layer 109. The thickness of the resist pattern 154 is about 1 μm. Next, a gold (Au) layer 110 of about 1 μm in thickness is formed on the seed layer 109 in each opening of the resist pattern 154 by electroplating.
Thereafter, as shown in FIG. 1L, the resist pattern 154 is removed.
Then, as shown in FIG. 1M, by ion-milling, a portion of the seed layer 109 exposed from the gold (Au) layer 110 is removed. The gold (Au) layer 110 is also processed a little simultaneously, and the resultant thickness of the gold (Au) layer 110 is about 0.6 μm.
Next, as shown in FIG. 1N, a surface protecting layer 111 is formed over the whole surface on the front side of the insulating substrate 101, and the front and the back of the insulating substrate 101 are inversed. Then, the thickness of the insulating substrate 101 is adjusted to about 150 μm by polishing the back surface of the insulating substrate 101.
Thereafter, as shown in FIG. 1O, a stacked body composed of a titanium (Ti) layer and a nickel (Ni) layer, or a titanium (Ti) layer and a copper (Cu) layer is formed as a seed layer 112 over the back of the insulating substrate 101. Then, a resist pattern 155 covering a part corresponding to the source electrode 104s is formed on the seed layer 112. The thickness of the resist pattern 155 is about 3 μm, and the diameter thereof is about 100 μm. Next, a nickel (Ni) layer 113 of about 3.2 μm in thickness is formed over the seed layer 112 in the area excepting the resist pattern 155 by electroplating.
Next, as shown in FIG. 1P, the resist pattern 155 is removed. Then, a portion of the seed layer 112 which is exposed from the nickel (Ni) layer 113 is removed by ion-milling. The nickel (Ni) layer 113 is simultaneously processed a little and the resultant thickness of the nickel (Ni) layer 113 is about 3 μm.
Thereafter, as shown in FIG. 1Q, a via hole 101s is formed by conducting dry etching of the insulating substrate 101 using the nickel (Ni) layer 113 as a mask. In the dry etching, a mixed gas of sulfur hexafluoride (SF6) gas and oxygen (O2) gas is used.
Then, as shown in FIG. 1R, the via hole 101s is allowed to reach the seed layer 107 by conducting dry etching of the GaN layer 102 and the n-type AlGaN layer 103 using the nickel (Ni) layer 113 as a mask. Chlorine gas (Cl2) is used for the dry etching. In the dry etching, the nickel (Ni) layer 108 and the seed layer 107 serve as an etching stopper.
Next, as shown in FIG. 1S, a resist layer 156 is formed in the via hole 101s and over the nickel (Ni) layer 113.
Next, as shown in FIG. 1T, the resist layer 156 is left only in the via hole 101s by conducting exposure and development of the resist layer 156.
Thereafter, as shown in FIG. 1U, the nickel (Ni) layer 113 and the seed layer 112 are removed by ion-milling.
Then, as shown in FIG. 1V, the resist layer 156 is removed. Next, a portion of the seed layer 107 which is exposed from the via hole 101s is removed by ion-milling. Then, a stacked body composed of a titanium (Ti) layer, a platinum (Pt) layer and a gold (Au) layer is formed as a seed layer 114 over the whole surface on the back side of the insulating substrate 101.
Next, as shown in FIG. 1W, a gold (Au) layer 115 of about 10 μm in thickness is formed over the seed layer 114 by electroplating.
As shown in FIG. 1X, the front and the back of the insulating substrate 101 are inversed and the surface protecting layer 111 is removed.
Conventionally, the GaN base HEMT has been manufactured by the method like this.
However, formation and extension processing of the via hole 101s are not easy with this conventional manufacturing method.
For example, the dry etching rate of the insulating substrate 101 made of SiC is subject to be influenced by the diameter or the like of the via hole 101s, and its in-plane distribution is great. Accordingly, conventionally, over-etching is conducted for the purpose of obtaining high yields by allowing the via hole 101s to reach the GaN layer 102 with reliability. The etching selection ratio of SiC to nickel (Ni) is 100 or more under the ordinary dry etching condition of the insulating substrate 101, however, the etching selection ratio among SiC, and GaN and AlGaN is as low as about 20 to 30. The total thickness of the GaN layer 102 and the n-type AlGaN layer 103 is as thin as about 2 μm. Accordingly, as a result of the over-etching, the variation in the ratio of remaining the GaN layer 102 and the n-type AlGaN layer 103 is greater. For example, when the variation (in-plane distribution) in the dry etching rate of the insulating substrate 101 is about ±5%, 33% of over-etching (corresponding to the etching amount of 50 μm in SiC thickness) is supposed to be conducted for the purpose of forming the via hole 101s of 150 μm in depth. The selection ratio between SiC, and GaN, AlGaN is supposed to be 25. In this case, though 0.4 μm of the GaN layer 102 remains in some portions, the GaN layer 102 and the n-type AlGaN layer 103 are completely removed in other portions. If dry etching of the remaining GaN layer 102 and the remaining n-type AlGaN layer 103 is conducted from this state, the seed layer 107 and the nickel (Ni) layer 108 cannot work as an etching stopper in the areas where the GaN layer 102 and the n-type AlGaN layer 103 has been completely removed, and these layers areas are still also etched. Since the thickness of the nickel (Ni) layer 108 is about 1 μm, the nickel (Ni) layer 108 might also be removed.
If the nickel (Ni) layer 108 is made thicker, it is possible to prevent the total removal, but in this case, other problems occur. That is, after forming the nickel (Ni) layer 108, formation of the resist pattern 154 is necessary for forming the gold (Au) layer 110 (FIG. 1K), but when the thickness of the nickel (Ni) layer 108 exceeds 1 μm, say about 3 μm for example, the thickness lacks its uniformity and distortion of the pattern easily occurs unless the resist pattern 154 is formed thickly. In other words, the opening precision of the pattern is apt to be lowered. Meanwhile, for the purpose of preventing this problem, if the resist pattern 154 is also formed thickly, it becomes difficult to form the resist pattern 154 with high resolution. Because of these circumstances, in the conventional manufacturing method, the thickness of the nickel (Ni) layer 108 is kept about 1 μm.
In the dry etching of the insulating substrate 101 (FIG. 1Q) and the dry etching of the GaN layer 102 and the n-type AlGaN layer 103 (FIG. 1R), the nickel (Ni) layer 113 is used as a metal mask. Accordingly, it is possible to conduct the two times of dry etching in the same chamber. However, in this case, sulfur hexafluoride (SF6) used in the dry etching of the insulating substrate 101 remains, and the etching rate of the GaN layer 102 and the n-type AlGaN layer 103 becomes unstable owing to this effect. FIG. 2 is a graph showing the result of an ICP dry etching experiment conducted by the present inventor for confirmation. ● in FIG. 2 shows the etching rate when only chlorine gas (Cl2) being an etching gas is supplied at a flow rate of 30 sccm, ♦ shows the etching rate when nitrogen gas (N2) is mixed with other than chlorine gas (Cl2) at 30 sccm, and ▴ shows the etching rate when sulfur hexafluoride (SF6) gas is mixed with other than chlorine gas (Cl2) at 30 sccm. In any measurement, the antenna power is set to 150 W and the bias power is set to 10 W. As shown in FIG. 2, when only chlorine gas (Cl2) is supplied, the etching rate of 54 nm/min is obtained, and even when diluting by mixing nitrogen gas (N2), the etching rate of about 40 nm/min can be obtained. Meanwhile, in the case that sulfur hexafluoride (SF6) gas is mixed, the etching rate is considerably reduced to 2 nm/min even when the flow rate is only 1 sccm. Thus, when even trace amount of sulfur hexafluoride (SF6) gas remains in the chamber, the etching rate of the GaN layer 102 and the n-type AlGaN layer 103 is considerably reduced. Accordingly, in the conventional method, evacuation to vacuum in a chamber or cleaning of the chamber with chlorine plasma is conducted before conducting the dry etching of the GaN layer 102 and the n-type AlGaN layer 103, which requires a longer time for the treatment. In addition, in order to shorten the treatment time, the treatments possible to be conducted in the same chamber (dry etching) are separately conducted with two sets of dry etching apparatuses, or conducted in two separate chambers using a dry etching apparatus provided with multi-chambers.
By conducting these means, it becomes possible to reduce the effect of sulfur hexafluoride (SF6) remaining in the chamber. When sulfur hexafluoride (SF6) is attached to the insulating substrate 101 or the like, however, it is difficult to exclude its influence.
See, for example Japanese Patent Application Laid-open Nos. 2004-363563 and 2004-327604.